Deep levels in metal-oxide-semiconductor capacitors fabricated on n-type In0.53Ga0.47As lattice matched to InP substrates

被引:4
|
作者
Simoen, E. [1 ,2 ]
Hsu, P-C [1 ,3 ]
Alian, A. [1 ]
El Kazzi, S. [1 ]
Wang, C. [4 ]
机构
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[2] Univ Ghent, Solid State Sci Dept, Krijgslaan 81, B-9000 Ghent, Belgium
[3] Katholieke Univ Leuven, Dept Mat Engn, B-3001 Leuven, Belgium
[4] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films Integrated Devices, Chengdu 610054, Sichuan, Peoples R China
关键词
DLTS; InGaAs; MOS capacitor; antisite defects; TRANSIENT SPECTROSCOPY; INTERFACE STATES; III-V; CONSTANT-CAPACITANCE; SI-SIO2; STRUCTURES; TRAPS; EL2; DEFECTS; RELAXATION; EMISSION;
D O I
10.1088/1361-6641/ab2481
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, deep levels present in n-type In0.53Ga0.47As hetero-epitaxial layers grown lattice-matched on n-type InP substrates by molecular beam epitaxy have been studied by deep-level transient spectroscopy (DLTS). Metal-oxide-semiconductor capacitors are employed, based on an Al2O3 gate oxide. It is shown that a single, near mid-gap electron trap dominates the DLT-spectra, whatever the surface pre-or post-gate oxide deposition treatment. At the same time, it is shown that the deep level parameters vary significantly from capacitor to capacitor and from wafer to wafer. Only after Forming Gas Annealing, a stable value for the activation energy of 0.39 +/- 0.01 eV is obtained. These results are tentatively interpreted in terms of antisite defects in the epitaxial layer, which form a family of related complexes with close deep-level parameters.
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页数:7
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