Cascading delay line time-to-digital converter with 75 ps resolution and a reduced number of delay cells

A time-to-digital converter (TDC) is described, integrated on a single field-programmable gate array device with 75 ps single-shot resolution (LSB). Multiple-shot measurement statistically improves resolution to about 5 ps. The circuit is based on a counter and a two-step cascading delay line method that uses only 24 delay cells to provide 128 LSBs in the interpolator that resolves the time interval within the reference clock cycle. The relevant calibration method is also presented to obtain the time parameters of the TDC at the current temperature and voltage. This TDC can measure time intervals from 0 to 1.3 ms and the maximum range is only limited by the range of the counter. The temperature dependence is 0.1 ps/degreesC. (C) 2005 American Institute of Physics.