Analysis of interconnection reliability of dielectric layer for wafer level chip scale package

被引：0

作者：

Wang, Chiyu ^{[1
]}

Hsieh, Adren ^{[1
]}

Wang, Yaochen ^{[1
]}

Pai, Archer ^{[1
]}

Pan, Cheng-Tang ^{[2
]}

Wang, Shao-Yu ^{[2
]}

Chiu, Chen-Chih ^{[2
]}

Wang, Bo-Sheng ^{[2
]}

Yang, Tsung-Lin ^{[2
]}

机构：

[1] Adv Semicond Engn, Kaohsiung, Taiwan

[2] Natl Sun Yat Sen Univ, Dept Mech & Electromech Engn, Kaohsiung 80424, Taiwan

来源：

2015 10TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study investigates of the mechanical properties of wafer level chip scale package (WLCSP) without under bump metallurgy (UBM) layer which is defined as 3-mask WLCSP package. The mechanical properties of dielectric layer, such as Young's modulus and hardness, were measured by nanoindentation systems. Simple models were developed to simulate the thermal stress and predict the failure area. In this study, the dielectric layer crack phenomena were examined. The nonlinear mechanical properties of dielectric layer measured by nanoindentation were used as the simulation parameters, based on which the thermal stress by simulation was obtained.

引用

页码：344 / 347

页数：4

共 5 条

[1] Design and optimization of thermo-mechanical reliability in wafer level packaging [J].