Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

被引:57
作者
Flachowsky, Stefan [1 ]
Wei, Andy [2 ]
Illgen, Ralf [1 ]
Herrmann, Tom [1 ]
Hoentschel, Jan [2 ]
Horstmann, Manfred [2 ]
Klix, Wilfried [1 ]
Stenzel, Roland [1 ]
机构
[1] Univ Appl Sci Dresden, Dept Elect Engn, D-01069 Dresden, Germany
[2] Globalfoundries Dresden Module One LLC & Co KG, D-01109 Dresden, Germany
关键词
CMOS; electrical field; MOSFET; mobility enhancement; SiGe; strain; strained overlayer film; strained silicon; strained silicon-on-insulator (sSOI); stress; stress memorization technique (SMT); DEEPLY SCALED NMOS; ELECTRON-MOBILITY; CARRIER-TRANSPORT; DRAIN-CURRENT; RESISTANCE; EXTRACTION; TRANSISTOR; VELOCITY; CMOS;
D O I
10.1109/TED.2010.2046461
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n- MOSFETs at low vertical fields. However, at high vertical fields, n- MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.
引用
收藏
页码:1343 / 1354
页数:12
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共 50 条
  • [1] Andrieu F, 2005, 2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P176
  • [2] Ang KW, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P1069
  • [3] Auth C., 2008, 2008 Symposium on VLSI Technology, P128, DOI 10.1109/VLSIT.2008.4588589
  • [4] Chen CH, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P56
  • [5] Chidambaram PR, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P48
  • [6] Performance degradation of small silicon devices caused by long-range Coulomb interactions
    Fischetti, MV
    Laux, SE
    [J]. APPLIED PHYSICS LETTERS, 2000, 76 (16) : 2277 - 2279
  • [7] On the enhanced electron mobility in strained-silicon inversion layers
    Fischetti, MV
    Gámiz, F
    Hänsch, W
    [J]. JOURNAL OF APPLIED PHYSICS, 2002, 92 (12) : 7320 - 7324
  • [8] 45nm SOICMOS technology with 3X hole mobility enhancement and asymmetric transistor for high performance CPU application
    Fung, Samuel K. H.
    Lo, H. C.
    Cheng, C. F.
    Lu, W. Y.
    Wu, K. C.
    Chen, K. H.
    Lee, D. H.
    Liu, Y. H.
    Wu, I. L.
    Li, C. T.
    Wu, C. H.
    Hsiao, F. L.
    Chen, T. L.
    [J]. 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 1035 - 1037
  • [9] Low temperature (≤ 800°C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS
    Gannavaram, S
    Pesovic, N
    Öztürk, MC
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 437 - 440
  • [10] GE CH, 2004, IEDM