Four-state stabilizing phase clock for unidirectional rings of odd size

被引：14

作者：

Huang, ST ^{[1
]}

Liu, TJ ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 30043, Taiwan

来源：

INFORMATION PROCESSING LETTERS | 1998年 / 65卷 / 06期

关键词：

clock synchronization; distributed systems; fault tolerance; self-stabilization;

D O I：

10.1016/S0020-0190(98)00006-4

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose a self-stabilizing binary phase clock protocol for unidirectional rings with odd size. The proposed protocol requires only four states for each processor and the worst-case stabilizing time is O(n(2)). This improves the previous result of 56 states and the worst-case stabilizing time of O(n(3)). (C) 1998 Elsevier Science B.V.

引用

页码：325 / 329

页数：5