Design of Reverse Converters for the New RNS Moduli Set {2n+1, 2n-1, 2n, 2n-1+1} (n odd)

被引:14
作者
Patronik, Piotr [1 ]
Piestrak, Stanislaw J. [2 ]
机构
[1] Wroclaw Univ Technol, Inst Comp Engn Control & Robot, PL-50370 Wroclaw, Poland
[2] Univ Lorraine, Fac Sci & Technol, Inst Jean Lamour, CNRS,Res Team MAE,UMR 7198, F-54506 Vandoeuvre Les Nancy, France
关键词
Application-specific integrated circuit (ASIC); Chinese remainder theorem (CRT); computer arithmetic; digital signal processing (DSP); residue arithmetic; residue number system (RNS); residue-to-binary converter; reverse converter; 4-MODULI SUPERSET 2(N)-1; HIGH-SPEED REALIZATION; RESIDUE NUMBER SYSTEM; BINARY; IMPLEMENTATION; REPRESENTATION; GENERATORS;
D O I
10.1109/TCSI.2014.2337237
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper considers a new balanced residue number system (RNS) composed of four low-cost moduli {2(n) + 1, 2(n) - 1, 2(n), 2(n-1) + 1} for odd. It is complementary to similar already known balanced 4-moduli set {2(n) + 1, 2(n) - 1, 2(n), 2(n+1) + 1} (odd), because it fills the gap in the sparse 8-bit resolution of dynamic ranges available for this class of 4-moduli RNSs. The first ever design methods of residue-to-binary (reverse) converters for this new RNS are proposed. Three versions of the converter, differing in the composition of calculations and hence resulting in different critical delays and energy consumption, are considered. Synthesis results obtained for the 65 nm technology for the dynamic ranges from 11 to 83 bits suggest that delay, power consumption, and area of the new converters are significantly improved w.r.t. the state-of-the-art converters for the above mentioned 4-moduli set and are comparable to those offered by the converters for two other balanced 4-moduli sets {2(n) + 1, 2(n) - 1, 2(n), 2(n +/- 1) + 1} (even).
引用
收藏
页码:3436 / 3449
页数:14
相关论文
共 37 条
[1]  
Abdallah M., 1995, Proceedings of the Twenty-Seventh Southeastern Symposium on System Theory, P445, DOI 10.1109/SSST.1995.390542
[2]   A reverse converter for the 4-moduli superset {2n-1, 2n, 2n+1, 2n+1+1} [J].
Bhardwaj, M ;
Srikanthan, T ;
Clarke, CT .
14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, :168-175
[3]   Efficient reverse converters for four-moduli sets {2n-1, 2n, 2n+1, 2n+1-1} and {2n-1, 2n, 2n+1, 2n-1-1} [J].
Cao, B ;
Srikanthan, T ;
Chang, CH .
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2005, 152 (05) :687-696
[4]   A residue-to-binary converter for a new five-moduli set [J].
Cao, Bin ;
Chang, Chip-Hong ;
Srikanthan, Thambipillai .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (05) :1041-1049
[5]  
Chalivendra G., 2011, P GREAT LAK S VLSI, P139, DOI 10.1145/1973009.1973038
[6]   Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures [J].
Chaves, R. ;
Sousa, L. .
IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (05) :472-480
[7]   Efficient Modulo 2n+1 Multipliers [J].
Chen, Jian Wen ;
Yao, Ruo He ;
Wu, Wei Jing .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (12) :2149-2157
[8]   Parallel-Prefix Ling Structures for Modulo 2n-1 Addition [J].
Chen, Jun ;
Stine, James. E. .
2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2009, :16-23
[9]  
Conway R, 2004, IEEE T CIRCUITS-II, V51, P26, DOI [10.1109/TCSII.2003.821524, 10.1109/tcsii.2003.821524]
[10]   Comments on "A high speed realization of a residue to binary number system converter" [J].
Dhurkadas, A .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (03) :446-447