High-precision Time-to-Digital Converter in a FPGA device

被引：5

作者：

Aloisio, A. ^{[1
,2
]}

Branchini, P. ^{[3
,4
]}

Giordano, R. ^{[1
,2
]}

Izzo, V. ^{[1
,2
]}

Loffredo, S. ^{[3
,4
]}

机构：

[1] Ist Nazl Fis Nucl, Dipartimento Sci Fis, Sez Napoli, I-80126 Naples, Italy

[2] Univ Naples Federico II, I-80126 Naples, Italy

[3] Univ Rome Tre, Dipartimento Fis, I-00146 Rome, Italy

[4] INFN Sezione Roma Tre, Dipartimento Fis, I-00146 Rome, Italy

来源：

2009 16TH IEEE-NPSS REAL TIME CONFERENCE | 2009年

关键词：

FPGA; TDC;

D O I：

10.1109/RTC.2009.5322005

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The construction and design process of a high-resolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision oil the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been performed.. one based on the phase information delivered by the VIRTEX-5 DCM and thus providing a rule time, a second level phase interpolation was based oil carry lines thus delivering an iper fine time measurement. We have designed and built a PCB hosting a Virtex-5 Xilinx FPGA. In this paper we show the main characteristics of the board and the performance achieved in terms of resolution.

引用

页码：283 / +

页数：2

共 5 条

[1] FPGA implementation of a high-resolution time-to-digital converter [J].

Aloisio, Alberto ;

Branchini, Paolo ;

Cicalese, Roberta ;

Giordano, Raffaele ;

Izzo, Vincenzo ;

Loffredo, Salvatore .

2007 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-11, 2007, :504-507

[2]

KALISZ J, METROLOGIS, V41, P17

[3] A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays [J].

Song, J ;

An, Q ;

Liu, SB .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (01) :236-241

[4]

2005, MVME6100 SERIES VME

[5]

2008, VIRTEX 5 USER GUIDE

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