A Study on Practically Unlimited Endurance of STT-MRAM

被引：76

作者：

Kan, Jimmy J. ^{[1
]}

Park, Chando ^{[1
]}

Ching, Chi ^{[2
]}

Ahn, Jaesoo ^{[2
]}

Xie, Yuan ^{[3
]}

Pakala, Mahendra ^{[2
]}

Kang, Seung H. ^{[1
]}

机构：

[1] Qualcomm Technol Inc, San Diego, CA 92121 USA

[2] Appl Mat Inc, Sunnyvale, CA 94085 USA

[3] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93111 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 09期

关键词：

Cache memory; practically unlimited endurance; spin-transfer torque magnetoresistive random-access memory (STT-MRAM); time-dependent dielectric breakdown (TDDB); unified memory; BREAKDOWN;

D O I：

10.1109/TED.2017.2731959

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project >10(15) write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cyclingendurance of STT-MRAM is "practically unlimited," which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches.

引用

页码：3639 / 3646

页数：8

共 19 条

[1] Barrier Breakdown Mechanisms in MgO-Based Magnetic Tunnel Junctions and Correlation With Low-Frequency Noise [J].