Detailed Analysis of the AES CTR Mode Parallel Execution Using OpenMP

被引：0
作者：
Ketata, Rim [1 ]
Kriaa, Lobna [1 ]
Saidane, Leila Azzouz [1 ]
Chalhoub, Gerard [2 ]
机构：
[1] Natl Sch Comp Sci ENSI, CRISTAL Lab RAMSIS Pole, Manouba, Tunisia
[2] Technol Univ Inst, LIMOS Lab, Networks & Protocols Team, Clermont Ferrand, France
来源：
5TH IFIP INTERNATIONAL CONFERENCE ON PERFORMANCE EVALUATION AND MODELING IN WIRED AND WIRELESS NETWORKS PEMWN 16 | 2016年
关键词：
AES; Counter mode; Parallelism; OpenMP; Parallel computing; Encryption;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Advanced Encryption Standard (AES), also known as the Rijndael algorithm, is a symmetric bloc cipher approved by the NIST institute and used for the encryption of electronic data. Thanks to its high level of security, AES is one of the most popular and widely adopted algorithms likely to be encountered nowadays in cryptographic systems. This level of security is reached by the application of a multitude of complex mathematical transformations on the input data. Thus, it requires a large amount of execution time which may not be feasible for some real time applications. In this paper we propose the parallelization of AES algorithm in Counter mode. The OpenMP API was chosen to parallelize the sequential code. We present a detailed analysis of the obtained results in terms of execution time and speed-up measurements.
引用
收藏
页数：9
相关论文
共 35 条
  • [31] Pendli V, 2016, 2016 2 INT C MOB SEC, P1
  • [32] OpenMP Task Scheduling Analysis via OpenMP Runtime API and Tool Visualization
    Qawasmeh, Ahmad
    Malik, Abid
    Chapman, Barbara
    [J]. PROCEEDINGS OF 2014 IEEE INTERNATIONAL PARALLEL & DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 2014, : 1050 - 1059
  • [33] AES algorithm implementation -: An efficient approach for sequential and pipeline architectures
    Saqib, NA
    Rodríguez-Henríquez, F
    Díaz-Pérez, A
    [J]. PROCEEDINGS OF THE FOURTH MEXICAN INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE (ENC 2003), 2003, : 126 - 130
  • [34] Tian Xinmin, P INT PAR DISTR PROC
  • [35] Celerity Hardware Implementation of the AES with Data Parallel and Pipelining Architecture inside the Round Function
    Yang, Shouwen
    Li, Hui
    Zhang, Xiaotao
    Zhao, Gang
    [J]. 2013 12TH IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS (TRUSTCOM 2013), 2013, : 1690 - 1695
1234