Side-Channel Attacks on Triple Modular Redundancy Schemes

Triple Modular Redundancy (TMR) is a well-known fault tolerance technique for avoiding errors in the Integrated Circuits (ICs) and it has been used in a wide range of applications. The TMR technique employs three instances of circuits realizing concurrently the same functionality whose outputs are compared through a majority voter. On the other hand, SideChannel Attacks (SCAs) are powerful techniques to extract secret information from ICs based on the data collected from security critical operations. Over the years, the interplay between security and reliability is poorly studied. In this paper, we explore the performance of SCAs on the well-known Advanced Encryption Standard (AES) and its different realizations using the TMR technique. In this work, three implementations of the AES design under the TMR scheme are used and an SCA, which can collect power dissipation data from the physical netlist through simulations, is developed. The experimental results show that the TMR technique can increase the computation time of SCAs and more importantly, the use of functionally equivalent, but physically and structurally different instances in the TMR scheme can make it impossible for SCAs to discover the secret key.