SOT-MRAM based Analog in-Memory Computing for DNN inference

被引：43

作者：

Doevenspeck, J. ^{[1
,2
]}

Garello, K. ^{[1
]}

Verhoef, B. ^{[1
]}

Degraeve, R. ^{[1
]}

Van Beek, S. ^{[1
]}

Crotti, D. ^{[1
]}

Yasin, F. ^{[1
]}

Couet, S. ^{[1
]}

Jayakumar, G. ^{[1
]}

Papistas, I. A. ^{[1
]}

Debacker, P. ^{[1
]}

Lauwereins, R. ^{[1
,2
]}

Dehaene, W. ^{[1
,2
]}

Kar, G. S. ^{[1
]}

Cosemans, S. ^{[1
]}

Mallik, A. ^{[1
]}

Verkest, D. ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

[2] KU Leuven ESAT, Leuven, Belgium

来源：

2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2020年

关键词：

D O I：

10.1109/vlsitechnology18217.2020.9265099

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Deep neural network (DNN) inference requires a massive amount of matrix-vector multiplications which can be computed efficiently on memory arrays in an analog fashion. This approach requires highly resistive memory devices (>MS 2) with low resistance variability to implement DNN weight memories. We propose an optimized Spin-Orbit Torque MRAM (SOTMRAM) as weight memory in Analog in-Memory Computing (AiMC) systems for DNN inference. In SOT-MRAM the write and read path are decoupled. This allows changing the MTJ resistance to the high levels required for AiMC by tuning the tunnel barrier thickness without affecting the writing. The target resistance level and variation are derived from an algorithm driven design-technology-co-optimization (DTCO) study. Resistance levels are obtained from IR-drop simulations of a convolutional neural network (CNN). Variation limits are obtained by testing two noise-resilient CNNs with conductance variability. Finally, we demonstrate experimentally that the requirements for analog DNN inference are met by SOT-MRAM stack optimization.

引用

页数：2