A K a-Band Dual-Mode Power Amplifier in 65-nm CMOS Technology

被引：15
|
作者：
Chang, Shuo-Hsuan [1 ]
Chen, Chun-Nien [1 ]
Wang, Huei [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Commun Engn, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2018年 / 28卷 / 08期
关键词：
CMOS; power amplifier; switched capacitor;
D O I：
10.1109/LMWC.2018.2844345
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this letter, a Ka-band dual-mode power amplifier with a new topology is fabricated in 65-nm standard CMOS. The PA with the switched capacitor to modulate the output impedance to match the optimal load impedance of the operation mode provides efficiency enhancement in low-output power region and costs smaller chip size. The PA demonstrates 19.9 dBm (17 dBm) P-sat, 25.8% (22.8%) PAE(max), 17 dBm (14 dBm) OP1dB, and 14.5% (17.4%) PAE(1dB) at 34 GHz in the high-power (low-power) mode. The total chip size of the dual-mode PA is only 0365 mm(2), including pads.
引用
收藏
页码：708 / 710
页数：3
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