Design considerations and comparative investigation of ultra-thin SOI, double-gate and cylindrical nanowire FETs

被引：0
|
作者：
Gnani, E. [1 ]
Reggiani, S. [1 ]
Rudan, M. [1 ]
Baccarani, G. [1 ]
机构：
[1] Univ Bologna, ARCES, Viale Risorgimento 2, I-40136 Bologna, Italy
来源：
ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2006年
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暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI), double-gate (DG) and cylindrical nanowire (CNW) FETs, with the aim of establishing optimization procedures and appropriate scaling rules towards their extreme miniaturization limits. The simulation model fully accounts for quantum electrostatics; current transport is modeled by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements. The simple rule resulting from this investigation is that stringent short-channel effect constraints can be fulfilled at a constant oxide thickness of 2 nm, with L-g/t(Si) approximate to 5 for the SOI-FET, L-g/t(Si) approximate to 2 for the DG-FET, and L-g/t(Si) approximate to 1 for the CNW-FET.
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页码：371 / +
页数：2
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