Circuit optimization via sequential computer experiments: design of an output buffer

被引:28
作者
Aslett, R
Buck, RJ
Duvall, SG
Sacks, J
Welch, WJ [1 ]
机构
[1] Univ Waterloo, Dept Stat & Actuarial Sci, Waterloo, ON N2L 3G1, Canada
[2] Intel Corp, Hillsboro, OR 97124 USA
[3] Western Michigan Univ, Kalamazoo, MI 49008 USA
[4] Intel Corp, Santa Clara, CA 95051 USA
[5] Natl Inst Stat Sci, Res Triangle Pk, NC USA
关键词
circuit simulator; computer code; computer model; engineering design; parameter design; stochastic process; visualization;
D O I
10.1111/1467-9876.00096
中图分类号
O21 [概率论与数理统计]; C8 [统计学];
学科分类号
020208 ; 070103 ; 0714 ;
摘要
In electrical engineering, circuit designs are now often optimized via circuit simulation computer models. Typically, many response variables characterize the circuit's performance. Each response is a function of many input variables, including factors that can be set in the engineering design and noise factors representing manufacturing conditions. We describe a modelling approach which is appropriate for the simulator's deterministic input-output relationships. Non-linearities and interactions are identified without explicit assumptions about the functional form. These models lead to predictors to guide the reduction of the ranges of the designable factors in a sequence of experiments. Ultimately, the predictors are used to optimize the engineering design. We also show how a visualization of the fitted relationships facilitates an understanding of the engineering tradeoffs between responses. The example used to demonstrate these methods, the design of a buffer circuit, has multiple targets for the responses, representing different trade-offs between the key performance measures.
引用
收藏
页码:31 / 48
页数:18
相关论文
共 19 条
[1]   APPLICATION OF STATISTICAL DESIGN AND RESPONSE-SURFACE METHODS TO COMPUTER-AIDED VLSI DEVICE DESIGN [J].
ALVAREZ, AR ;
ABDI, BL ;
YOUNG, DL ;
WEED, HD ;
TEPLIK, J ;
HERALD, ER .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (02) :272-288
[2]  
Bates RA, 1996, J ROY STAT SOC B MET, V58, P77
[3]   INTEGRATED-CIRCUIT DESIGN OPTIMIZATION USING A SEQUENTIAL STRATEGY [J].
BERNARDO, MC ;
BUCK, R ;
LIU, LS ;
NAZARET, WA ;
SACKS, J ;
WELCH, WJ .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1992, 11 (03) :361-372
[4]  
BOX GEP, 1959, J AM STAT ASSOC, V54, P622
[5]   A SURVEY OF OPTIMIZATION TECHNIQUES FOR INTEGRATED-CIRCUIT DESIGN [J].
BRAYTON, RK ;
HACHTEL, GD ;
SANGIOVANNIVINCENTELLI, AL .
PROCEEDINGS OF THE IEEE, 1981, 69 (10) :1334-1362
[6]   BAYESIAN PREDICTION OF DETERMINISTIC FUNCTIONS, WITH APPLICATIONS TO THE DESIGN AND ANALYSIS OF COMPUTER EXPERIMENTS [J].
CURRIN, C ;
MITCHELL, T ;
MORRIS, M ;
YLVISAKER, D .
JOURNAL OF THE AMERICAN STATISTICAL ASSOCIATION, 1991, 86 (416) :953-963
[7]  
Gill P., 1986, 862 SOL STANF U DEP
[8]  
Hastie T., 1990, Generalized additive model
[9]   A DISTRIBUTION-FREE APPROACH TO INDUCING RANK CORRELATION AMONG INPUT VARIABLES [J].
IMAN, RL ;
CONOVER, WJ .
COMMUNICATIONS IN STATISTICS PART B-SIMULATION AND COMPUTATION, 1982, 11 (03) :311-334
[10]   A COMPARISON OF THREE METHODS FOR SELECTING VALUES OF INPUT VARIABLES IN THE ANALYSIS OF OUTPUT FROM A COMPUTER CODE [J].
MCKAY, MD ;
BECKMAN, RJ ;
CONOVER, WJ .
TECHNOMETRICS, 1979, 21 (02) :239-245