Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

被引：20

作者：

Lin, XN ^{[1
]}

Feng, CG ^{[1
]}

Zhang, SD ^{[1
]}

Ho, WH ^{[1
]}

Chan, MS ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China

来源：

SOLID-STATE ELECTRONICS | 2004年 / 48卷 / 12期

关键词：

SOI MOSFET; double gate; recrystallization;

D O I：

10.1016/j.sse.2004.04.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILL). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices. (C) 2004 Elsevier Ltd. All rights reserved.

引用

页码：2315 / 2319

页数：5

共 12 条

[1] CHAN VWC, P 2001 INT SOI C, P112
[2] Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization
Cheng, CF
Poon, VMC
Kok, CW
Chan, MS
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (06) : 1467 - 1474
[3] Fully depleted dual-gated thin-film SOI P-MOSFET's fabricated in SOI islands with an isolated buried polysilicon backgate
Denton, JP
Neudeck, GW
[J]. IEEE ELECTRON DEVICE LETTERS, 1996, 17 (11) : 509 - 511
[4] Performance of thin-film transistors with ultrathin Ni-MILC polycrystalline silicon channel layers
Jin, ZH
Kwok, HS
Wong, M
[J]. IEEE ELECTRON DEVICE LETTERS, 1999, 20 (04) : 167 - 169
[5] Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
Kim, K
Fossum, JG
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (02) : 294 - 299
[6] PAE S, 1999, IEES SOI C OCT
[7] PARK JT, 2001, IEEE SOI C OCT
[8] SCALING THEORY FOR DOUBLE-GATE SOI MOSFETS
SUZUKI, K
TANAKA, T
TOSAKA, Y
HORIE, H
ARIMOTO, Y
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (12) : 2326 - 2329
[9] TAUR Y, 1999, INT S VLSI TECHN SYS, P6
[10] Super thin-film transistor with SOICMOS performance formed by a novel grain enhancement method
Wang, HM
Chan, MS
Jagar, S
Poon, VMC
Qin, M
Wang, YY
Ko, PK
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (08) : 1580 - 1586

← 1 2 →