Cascaded multilevel inverter based on ladder bridges: Analysis, optimization, and implementation

This paper proposes a new ladder-switch based cascaded multilevel inverter that requires a lower number of insulated gate bipolar transistors (IGBTs) and direct current (DC) voltage sources to generate a specified range of voltage levels. Regarding this topology, it consists of lambda stages, where each stage comprises k legs, besides each leg composed of n cells. So, the proposed topology can be optimized to obtain the lower requirement for IGBTs and DC voltage sources. It is required to mention that this topology generates both negative and positive voltage levels inherently. Two different algorithms are presented to synthesize all odd and even voltage levels. After, regarding each of the algorithms, the proposed topology is optimized from different aspects of the lowest number of IGBTs or the lowest number of DC voltage sources, and results are depicted. A comparison assessment is performed to find the advantages and possible disadvantages of the proposed topology. In the end, a 23-level prototype of the proposed topology is used to validate the correct performance of the proposed topology using the experimental results.