A constraint-based stack generation technique for CMOS analog circuits

This paper proposes a new technique to automatically generate sets of CMOS transistor stacks from spice net-list based on the specified analog constraints. To facilitate the stack generation, the symmetry structures and matching components are automatically extracted from circuit net-list, which will be used to force the symmetry and matching layout. A diffusion graph is employed to represent the connectivity of the CMOS circuits. Based on this graph, an efficient stack generation algorithm is proposed to optimize the stack shape, area and parasitic capacitance simultaneously.