Bias stress stability of asymmetric source-drain a-Si:H thin film transistors

The threshold voltage (V-T) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the. absence of a drain bias (V-G=15V, V-D=0V), the threshold voltage (V-T) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (V-G=15V, V-D=20V), the V-T shifts of asymmetric TFTs were less than symmetric TFT. The V-T shifts of 'L' and 'J' shaped TFT were 0.29V, 0.24V respectively, while the V-T shift of 'I' shaped TFT was 0.42V. The less V-T degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less V-T degradation compared with the symmetric TFT.