Modeling and parameter extraction methods of bond-wires for chip-package co-design

被引:0
|
作者
Jing, Weiping [1 ]
Sun, Ling [1 ]
Sun, Haiyan [1 ]
机构
[1] Nantong Univ, Jiangsu Provincial Key Lab ASIC Design, No 40 Qingnian Rd E, Nantong, Peoples R China
来源
ICEPT: 2006 7TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS | 2006年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The objective of this paper was to present a preparatory investigation of modeling of IC packages for chip-package co-design. Our work was focused on the modeling and Parameter extraction methods of bond-wires. Based on two-port parameters, a lumped II-type equivalent circuit for a single-bond-wire was presented and the R, L, and C parameters of the bond-wire were extracted. In addition, multi-bond-wires were proposed for better performance by comparing their simulated S-parameters with measured results. Finally, a simple and low cost test structure was designed and made for validation of the parameterized model.
引用
收藏
页码:173 / +
页数:2
相关论文
共 50 条
  • [1] Characterisation, modelling and design of bond-wire interconnects for chip-package co-design
    Chandrasekhar, A
    Stoukatch, S
    Brebels, S
    Balachandran, J
    Beyne, E
    De Raedt, W
    Nauwelaers, B
    Poddar, A
    33RD EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, 2003, : 301 - 304
  • [2] Chip-package co-design of a 4.7 GHz VCO
    Donnay, S
    Vaesen, K
    Pieters, P
    Diels, W
    Wambacq, P
    de Raedt, W
    Beyne, E
    Engels, M
    ICM'99: ELEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, 1999, : 145 - 148
  • [3] Chip-package co-design of a 4.7 GHz VCO
    Vaesen, K
    Donnay, S
    Pieters, P
    Carchon, G
    Diels, W
    Wambacq, P
    De Raedt, W
    Beyne, E
    Engels, M
    Bolsens, I
    2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 301 - 306
  • [4] System Aware Floorplanning for Chip-Package Co-design
    Pan, Tse-Han
    Franzon, Paul D.
    Srinivas, Vaishnav
    Nagarajan, Mahalingam
    Popovic, Darko
    2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,
  • [5] Analysis of VCO jitter in chip-package co-design
    Parthasarathy, H
    Nayak, G
    Mukund, PR
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 181 - 184
  • [6] CHIP-PACKAGE CO-DESIGN: EFFECT OF SUBSTRATE WARPAGE ON BEOL RELIABILITY
    Raghavan, Sathyanarayanan
    Schmadlak, Ilko
    Leal, George
    Sitaraman, Suresh
    PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION, 2013, VOL 10, 2014,
  • [7] Routability-Driven Bump Assignment for Chip-Package Co-Design
    Chen, Meng-Ling
    Tsai, Tu-Hsiung
    Chen, Hung-Ming
    Chen, Shi-Hao
    2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 519 - 524
  • [8] Chip-package co-design of power distribution network for system-in-package applications
    Kim, GW
    Kam, DG
    Chung, DH
    Kim, JH
    6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 499 - 501
  • [9] Upper/Lower boundary estimation of package interconnect parasitics for chip-package co-design
    Song, Eunseok
    Lee, Heeseok
    Leet, Jungtae
    Jin, Woojin
    Choi, Kiwon
    Yang, Sa-Yoon
    ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2007, : 573 - +
  • [10] Chip-package co-design for high performance and reliability off-chip communications
    Shen, M
    Liu, J
    Zheng, LR
    Tenhunen, H
    PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), 2004, : 31 - 36