A Continuous-Time ΔΣ Modulator with a Digital Technique for Excess Loop Delay Compensation

被引：0

作者：

Zhang, Yi ^{[1
]}

Chen, Chia-Hung ^{[1
]}

He, Tao ^{[1
]}

Meng, Xin ^{[1
]}

Temes, Gabor C. ^{[1
]}

机构：

[1] Oregon State Univ, Sch EECS, Corvallis, OR 97331 USA

来源：

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2014年

关键词：

excess loop delay; reference switching; FIR feedback DAC; ADC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3rd-order continuous-time Delta Sigma modulator with a highly-digital technique for excess loop delay (ELD) compensation is reported. A digitally controlled reference switching matrix is used to replace the commonly used power-hungry signal adder and extra DAC driving the quantizer. The feedback DAC is embedded in the quantizer, and implemented by a few switches. The proposed technique helps the modulator tolerate excess loop delay up to half a clock period. The modulator achieves an SQNR of 83.3 dB in a 15 MHz signal bandwidth. The use of a 2-bit FIR feedback DAC lowers the jitter-induced noise by about 10 dB. The simulated power consumption of the modulator is 7 mW.

引用

页码：934 / 937

页数：4

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