Low-cost space-borne processing on a reconfigurable parallel architecture

被引:0
|
作者
Bretschneider, T [1 ]
Ramesh, B [1 ]
Gupta, V [1 ]
McLoughlin, I [1 ]
机构
[1] Nanyang Technol Univ, Satellite Engn Ctr, Singapore 639798, Singapore
来源
ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS | 2004年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a reconfigurable parallel architecture for space-borne on-board processing that combines the advantages of powerful computational resources with a straightforward software development. This approach introduces the concept of software payloads that enable the users the direct transfer of their ground-based applications towards space and thus the circumvention of the usual downlink bottleneck. The main emphasis is on the processing model and the software development aspect. The advantages in the proposed system are highlighted by a series of demonstration applications. A trade-off analysis of these suggested processing tasks with respect to a ground-based solution concludes the investigation.
引用
收藏
页码:93 / 99
页数:7
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