A State Machine Encoding Methodology Against Power Analysis Attacks

被引:1
作者
Agrawal, Richa [1 ]
Vemuri, Ranga [1 ]
Borowczak, Mike [2 ]
机构
[1] Univ Cincinnati, Sch Elect & Comp Syst, Digital Design Environm Lab, Cincinnati, OH 45221 USA
[2] Univ Wyoming, Coll Engn & Appl Sci, Dept Comp Sci, Laramie, WY 82071 USA
来源
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2019年 / 35卷 / 05期
关键词
Low power; Finite state controllers; Power analysis; Satisfiability checking; Boolean constraints; SIDE; LOGIC;
D O I
10.1007/s10836-019-05821-z
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Power side-channel attacks have been shown to be effective against recovering protected information from integrated circuits. Existing defense methods are expensive in area, power or both. Small-scale ICs used in embedded systems and IoT devices are expected to be safe and secure, and yet cannot afford the area and power overheads of the sophisticated defense methods. This paper presents a design methodology for finite state controllers (FSMs) to defend against power analysis attacks while ensuring low power overhead. Further, a desired level of security can be achieved while minimizing power consumption. We formulate a set of constraints on state encoding based on security and power metrics. We express these constraints as a Boolean satisfiability (SAT) problem and use a SAT solver to generate constraint satisfying encodings. Experimental results using over 100 FSMs from BenGen and MCNC benchmark suites show a graded increase in encoding length (up to 40% for original FSMs and 40-70% for restructured FSMs) depending on the security level chosen. Trade-off between security and power is demonstrated as the mutual information between power side-channel and the Hamming attack models can vary between 0 and 2, depending on the level of security desired. An average power reduction of up to 40% is observed in power-constrained FSMs with respect to restructured FSMs and 4-20% reduction with respect to minimal encoding strategy.
引用
收藏
页码:621 / 639
页数:19
相关论文
共 42 条
[1]   A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration [J].
Agrawal, Richa ;
Borowczak, Mike ;
Vemuri, Ranga .
2019 32ND INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2019 18TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2019, :70-75
[2]  
Agrawal R, 2018, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), P181, DOI 10.1109/HST.2018.8383911
[3]  
Akkar ML, 2000, LECT NOTES COMPUT SC, V1976, P489
[4]  
Aljazeera K. R., 2016, 2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), P166, DOI 10.1109/SCOPES.2016.7955732
[5]  
Ambrose JA, 2015, INT SYM QUAL ELECT, P447
[6]  
[Anonymous], 2005, IACR Cryptol. EPrint Arch
[7]  
[Anonymous], 2008, POWER ANAL ATTACKS R
[8]  
Bahnasawi MA, 2016, INT C MICROELECTRON, P285, DOI 10.1109/ICM.2016.7847871
[9]   Enabling Side Channel Secure FSMs in the presence of Low Power Requirements [J].
Borowczak, Mike ;
Vemuri, Ranga .
2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, :233-236
[10]   S*FSM: AParadigm Shift for Attack Resistant FSM Designs and Encodings [J].
Borowczak, Mike ;
Vemuri, Ranga .
2012 ASE INTERNATIONAL CONFERENCE ON BIOMEDICAL COMPUTING (BIOMEDCOM), 2012, :96-100