A novel low-power FPGA routing switch

被引：16

作者：

Anderson, JH ^{[1
]}

Najm, FN ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358930

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a new programmable FPGA routing switch that can operate in three different modes: high-speed, low-power or sleep. High-speed mode offers similar power and performance to a traditional routing switch. In low-power mode, power is reduced at the expense of speed. Leakage power is reduced by 36-40% in low-power vs. high-speed mode (on average); dynamic power is reduced by up to 28%. Leakage power in sleep mode is 61% lower than in high-speed mode. The applicability of the new switch is motivated through an analysis of timing slack in industrial FPGA designs. Specifically, we show that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.

引用

页码：719 / 722

页数：4

共 50 条

[41] Nonvolatile Programmable Switch With Adjacently Integrated Flash Memory and CMOS Logic for Low-Power and High-Speed FPGA [J].

Zaitsu, Koichiro ;

Tatsumura, Kosuke ;

Matsumoto, Mari ;

Oda, Masato ;

Yasuda, Shinichi .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (12) :4009-4014

[42] A Novel SPDT Rotary RF MEMS Switch for Low Loss and Power Efficient Signal Routing [J].

Ilkhechi, Afshin Kashani ;

Mirzajani, Hadi ;

Aghdam, Esmaeil Najafi ;

Ghavifekr, Habib Badri .

IETE JOURNAL OF RESEARCH, 2016, 62 (01) :68-80

[43] Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA [J].

Banno, Naoki ;

Okamoto, Koichiro ;

Iguchi, Noriyuki ;

Ochi, Hiroyuki ;

Onodera, Hidetoshi ;

Hashimoto, Masanori ;

Sugibayashi, Tadahiko ;

Sakamoto, Toshitsugu ;

Tada, Munehiro .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (08) :3331-3336

[44] Designing an Asynchronous FPGA Processor for Low-Power Sensor Networks [J].

Liu, Yijun ;

Xie, Guobo ;

Chen, Pinghua ;

Chen, Jingyu ;

Li, Zhenkun .

ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,, 2009, :261-265

[45] Low-power high-level synthesis for FPGA architectures [J].

Chen, DM ;

Cong, J ;

Fan, YP .

ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2003, :134-139

[46] Low-Power Ultrasound Imaging on Mixed FPGA/GPU Systems [J].

Cacko, Damian ;

Walczak, Mateusz ;

Lewandowski, Marcin .

2018 JOINT CONFERENCE - ACOUSTICS, 2018, :42-47

[47] Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA [J].

Pham, Thinh H. ;

Fahmy, Suhaib A. ;

McLoughlin, Ian Vince .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (08) :1549-1553

[48] Low-Power FPGA Based Security System For Cabinet Protection [J].

Gopikrishna, P. V. ;

Kamath, Harsh ;

Sogolad, Prasad ;

Kulkarni, G. H. .

FIRST INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, TECHNOLOGY AND SCIENCE - ICETETS 2016, 2016,

[49] Synthesis of low-power synchronous controllers using FPGA implementation [J].

Oliveira, Duarte L. ;

Salazar, Alexis F. T. ;

Romano, Leonardo .

2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2008, :221-+

[50] A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating [J].

Ishihara, Shota ;

Hariyama, Masanori ;

Kameyama, Michitaka .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (08) :1394-1406

← 1 2 3 4 5 →