A novel low-power FPGA routing switch

被引：16

作者：

Anderson, JH ^{[1
]}

Najm, FN ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358930

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a new programmable FPGA routing switch that can operate in three different modes: high-speed, low-power or sleep. High-speed mode offers similar power and performance to a traditional routing switch. In low-power mode, power is reduced at the expense of speed. Leakage power is reduced by 36-40% in low-power vs. high-speed mode (on average); dynamic power is reduced by up to 28%. Leakage power in sleep mode is 61% lower than in high-speed mode. The applicability of the new switch is motivated through an analysis of timing slack in industrial FPGA designs. Specifically, we show that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.

引用

页码：719 / 722

页数：4

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