Cointegration of high-performance tied-gate three-terminal FinFETs and variable threshold-voltage independent-gate four-terminal FinFETs with asymmetric gate-oxide thicknesses

被引：44

作者：

Liu, Yongxun ^{[1
]}

Matsukawa, Takashi ^{[1
]}

Endo, Kazuhiko ^{[1
]}

Masahara, Meishoku ^{[1
]}

O'uchi, Shin-ichi ^{[1
]}

Ishii, Kenichi ^{[1
]}

Yamauchi, Hiromi ^{[1
]}

Tsukada, Junichi ^{[1
]}

Ishikawa, Yuki ^{[1
]}

Suzuki, Eiichi ^{[1
]}

机构：

[1] Natl Inst Adv Ind Sci & Technol, Tsukuba 3058568, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2007年 / 28卷 / 06期

关键词：

asymmetric gate-oxide thicknesses; cointegration; double-gate MOSFET; FinFET; independent-gate FinFET; threshold-voltage control; TiN gate;

D O I：

10.1109/LED.2007.896898

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cointegration of titanium nitride (TiN)-gate highperformance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses (t(ox1) = t(ox2) = 1.7 nm) and variable threshold-voltage V-th independent-gate four-terminal (4T) FinFETs with asymmetric gate-oxide thicknesses (t(ox1) = 1.7 nm for the driving-gate-oxide, and t(ox2) = 3.4 or 7.0 nm for the control-gate-oxide) has been successfully developed using conventional reactive sputtering, two-step Si-fin and gate-oxide formation, and resist etch-back processes. A significantly improved subthreshold slope and an extremely low OFF-state current I-off are experimentally confirmed in,the asymmetric gate-oxide thickness 4T FinFETs by increasing the control-gate-oxide thickness to twice or more the driving-gate-oxide thickness. The developed techniques are attractive for high-performance and low-power FinFET very large-scale integration circuits.

引用

页码：517 / 519

页数：3

共 9 条

[1] High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices [J].

Chiang, Meng-Hsueh ;

Kim, Keunwoo ;

Chuang, Ching-Te ;

Tretz, Christophe .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (09) :2370-2377

[2] Improved independent gate N-type FinFET fabrication and characterization [J].

Fried, DM ;

Duster, JS ;

Kornegay, KT .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (09) :592-594

[3]

Hisamoto D, 2000, IEEE T ELECTRON DEV, V47, P2320, DOI 10.1109/16.887014

[4]

Liu YX, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P986

[5] Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching [J].

Liu, YX ;

Ishii, K ;

Tsutsumi, T ;

Masahara, M ;

Suzuki, E .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (07) :484-486

[6] Demonstration, analysis, and device design considerations for independent DG MOSFETs [J].

Masahara, M ;

Liu, YX ;

Sakamoto, K ;

Endo, K ;

Matsukawa, T ;

Ishii, K ;

Sekigawa, T ;

Yamauchi, H ;

Tanoue, H ;

Kanemaru, S ;

Koike, H ;

Suzuki, E .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (09) :2046-2053

[7]

MASAHARA M, 2006, P IEEE INT SOI C, P165

[8]

Mathew L, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P200

[9] Independent component analysis of EEG signals [J].

Sun, LS ;

Liu, Y ;

Beadle, PJ .

PROCEEDINGS OF 2005 IEEE INTERNATIONAL WORKSHOP ON VLSI DESIGN AND VIDEO TECHNOLOGY, 2005, :219-222

← 1 →