Chaos in delay locked loop

被引：0

作者：

Wang, Ping-Ying ^{[1
]}

Chou, C-H ^{[1
]}

Kao, Hsueh-Wu ^{[1
]}

机构：

[1] MediaTek Inc, Analog Circuit Design Div, Hsinchu, Taiwan

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We prove existence of chaos in delay locked loops (DLL). It is the first time that the chaotic phenomenon in DLLs is reported. The DLL is designed to verify predictions of theory analysis. The prediction of the theory is confirmed by circuits simulation. The chip size is only 0.015mm(2), thus provides a low cost analog solution to randomize clock phases and simple circuits to study chaos.

引用

页码：229 / +

页数：2

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