Rapid Low Power Voltage Level Shifter Utilizing Regulated Cross Coupled Pull Up Network

被引：0

作者：

kiran, Sai N. ^{[1
]}

Vignesh, N. Arun ^{[1
]}

Kanithan, S. ^{[2
]}

Sravani, K. ^{[1
]}

Kumari, Ch Usha ^{[1
]}

Swathi, K. ^{[1
]}

Kumareshan, N. ^{[3
]}

Nair, Prajith Prakash ^{[4
]}

机构：

[1] Gokaraju Rangaraju Inst Engn & Technol, Dept ECE, Hyderabad, India

[2] MVJ Coll Engn, Dept ECE, Bengaluru, India

[3] Sri Shakthi Inst Engn & Technol, Dept ECE, Coimbatore, Tamil Nadu, India

[4] ACS Coll Engn, Dept ECE, Bengaluru, India

来源：

2021 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS (ICCCI) | 2021年

关键词：

Level Shifter; Sub Threshold Voltage; Differential Cascode Voltage Switch; Less Power; SUBTHRESHOLD; CMOS;

D O I：

10.1109/ICCCI50826.2021.9402273

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this concise, ultra low power and high speed voltage or logic LS circuit is introduced. With the help of regulated cross coupled structure in the pull up region the power utilized by the circuit is considerably decreased and speed of the circuit is also increased. The LS can convert the input logic levels or voltages below the V-TH of the transistor to the higher acceptable levels. A LS requires less area because it consists of less number of components which makes it fit for low power and high speed applications, for example implantable clinical gadgets and remote sensor organizations. Tool used for simulation is LTspice 180nm technology. The LS can shift the input voltage or logic levels as less as 80mv to higher acceptable levels. The power utilized by LS is 149.5nw and propagation delay is 23.7ns.

引用

页数：9

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