FPGA Design and Implementation of Digital Up-Converter using Quadrature Oscillator

被引：0
作者：
de Figueiredo, Felipe Augusto P. [1 ]
Filho, Jose Arnaldo B. [1 ]
Lenzi, Karlo G. [1 ]
机构：
[1] CPqD Res & Dev Ctr Telecommun, Campinas, SP, Brazil
来源：
2013 IEEE JORDAN CONFERENCE ON APPLIED ELECTRICAL ENGINEERING AND COMPUTING TECHNOLOGIES (AEECT) | 2013年
关键词：
Digital Up Converter (DUC); Field-Programmable Gate Array (FPGA); Polyphase filter; Complex Multiplier; Quadarture Oscillator; Virtex6;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In this paper we design and implement a complex Digital Up-Converter (DUC) using a Xilinx Virtex6 FPGA. All the steps necessary to build such circuits are thoroughly described and some valuable hints on how to overcome problems during the design time are presented. We introduce a new approach for oscillator circuits, which are an important part of any DUC design. Such oscillator approach is stable, clean, accurate and easily tunable. It is also RAM memory efficient, consuming no block RAM and a small amount of logic.
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页数：7
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