A 0.8-V 1.7-μW 25.9-fJ Continuous-Time Sigma-Delta Modulator for Biomedical Applications

A low-voltage low-power 3th-order continuous-time (CT) sigma-delta (Sigma Delta) modulator is presented in this paper for biomedical applications. In order to lower the power consumption, a new loop filter with a single-opamp resonator, a 4-bit asynchronous successive-approximation register (SAR) analog-to-digital converter (ADC) and a capacitance digital-toanalog converter (CDAC) have been employed. The single-opamp combined with the passive elements can benefit the power consumption as well as the stability. The feedforward compensation scheme is employed to further reduce the power consumed by opamp, and the chopper stabilization technique is used to eliminate the 1/f noise. Moreover, the multi-bit SAR ADC and the DAC reduce the effects caused by clock jitter and thus improve the signal-to-noise ratio (SNR). The S.-modulator is designed in a 0.18 mu m CMOS process, which totally consumes 1.7 mu W in a 0.8V supply with 50KS/s sampling rate and results in a FOM of 25.9fJ/conversion. Within the 500 Hz bandwidth, the circuit achieves peak SNR of 104.5dB, SFDR of 114.0dB and DR of 72dB, respectively.