Real Time Discrete Wavelet Transform Architecture for Self Mixing Interferometry Signal Processing

被引:0
作者
Hussain, Syed Shahzad [1 ]
Zabit, Usman [1 ]
Bernal, Olivier D. [2 ]
机构
[1] Riphah Int Univ, Fac Engn & Appl Sci, Islamabad, Pakistan
[2] Univ Toulouse, CNRS, LAAS, INPT, 7 Ave Colonel Roche, Toulouse, France
来源
PROCEEDINGS OF 2017 14TH INTERNATIONAL BHURBAN CONFERENCE ON APPLIED SCIENCES AND TECHNOLOGY (IBCAST) | 2017年
关键词
Self mixing; optical feedback interferometry; wavelet transform; FPGA; FEEDBACK INTERFEROMETRY; SENSOR;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper describes the hardware implementation of forward discrete wavelet transform for self-mixing interferometry (SMI) signal processing. SMI signals are observed when the laser beam is backscattered after striking the target object and enter into the laser cavity thereby mixing with generated optical beam. The resulting SMI signal carries information about the remote target, so in order to retrieve the information (distance, displacement, velocity and vibration etc), SMI signal needs to be processed. Under stationary conditions, conventional Fourier transform can be used but when the conditions become non-stationary, wavelet transform based processing becomes a suitable choice. In this paper, we pro pose the forward wavelet architecture for real time processing of SMI signals so that target displacement can be measured with a precision of lambda/10, where lambda is the laser wavelength. The purpose of this research work is to implement the DWT based SMI signal processing algorithm in hardware so that real time displacement measurements can be retrieved from SMI signal with high precision. The proposed architecture comprises of eight processing elements using pipeline technique, where each processing element (PE) consists of two sub blocks, FIR filtering and Down sampler. The filter coefficients are pre-calculated and stored in the ROM. Simulation have been done on Xilinx ISIM (R) using Verilog HDL. Implementation is done on Spartan 3A FPGA, XC3S1400 (device), FG484 (package), -5 (grade speed). After implementation the synthesis results show that our proposed design is capable of operating at 605.76 MHz with minimum clock period of 1.651ns. Our design consumes 6651 slices, 2062 slice flip flops and 11232 4-input Lookup tables. The FPGA based algorithm implementation makes the SMI sensor more attractive, as it potentially allows to execute all signal processing by embedding it on the same board resulting in a fast, real-time and autonomous SM sensor.
引用
收藏
页码:323 / 327
页数:5
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