A fast lock digital phase-locked-loop architecture for wireless applications

被引：15

作者：

Fahim, AM ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 2003年 / 50卷 / 02期

关键词：

digital phase-locked loop (PLL); phase-locked loops (PLLs); wireless communications;

D O I：

10.1109/TCSII.2003.809711

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fast lock digital phase-locked-loop (PLL) frequency synthesizer for wireless applications is reported. The main advantages of the architecture include small area and digitally selectable frequency resolution. Also, a fully digital solution to reducing the phase lock time is introduced. This work is also supported by a nonlinear analytical analysis of the locking mechanism for PLLs.

引用

页码：63 / 72

页数：10

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