3D multi-layer vision architecture for surveillance and reconnaissance applications

被引：4

作者：

Foeldesy, Peter ^{[1
]}

Carmona-Galan, Ricardo ^{[2
]}

Zarandy, Akos ^{[1
]}

Rekeczky, Csaba ^{[3
]}

Rodriguez-Vazquez, Angel ^{[4
]}

Roska, Tamas ^{[1
]}

机构：

[1] Hungarian Acad Sci, Comp & Automat Res Inst, MTA SZTAKI, Budapest, Hungary

[2] IMSE, CNM, Seville, Spain

[3] Eutecus Inc, Berkeley, CA USA

[4] AnaFocus, Seville, Spain

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

D O I：

10.1109/ECCTD.2009.5274944

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The architecture and the design details of a multi-layer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320x240 sensor array layer, closely coupled with a 160x120 mixed-signal processor array layer, a digital frame buffer layer, and an 8x8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS.

引用

页码：185 / +

页数：2