Low power bus coding techniques considering inter-wire capacitances

被引：74

作者：

Sotiriadis, PP ^{[1
]}

Chandrakasan, A ^{[1
]}

机构：

[1] MIT, Dept EECS, Cambridge, MA 02139 USA

来源：

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年

关键词：

D O I：

10.1109/CICC.2000.852719

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The power dissipation associated with driving data busses can be significant, especially considering the increasing component of inter-wire capacitance. Previous work on bus encoding has focused on minimizing transitions to reduce power dissipation. In this paper, it is shown that transition reduction is not necessarily the best approach for reducing power when the effects of inter-wire capacitance are considered. An electrical model for data busses designed with submicron technologies is presented and a family of coding techniques is proposed that can reduce the average power consumption of the bus by 40%.

引用

页码：507 / 510

页数：4

共 10 条

[1]

BISHOP B, 1999, INT S LOW POW EL DES, P85

[2]

CHANDRAKASAN A, 1998, LOW POWER MCOS DESIG

[3] DATA-DEPENDENT LOGIC SWING INTERNAL BUS ARCHITECTURE FOR ULTRALOW-POWER LSIS [J].