A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55-nm CMOS

被引：10

作者：

Chung, Yung-Hui ^{[1
]}

Rih, Wei-Shu ^{[1
]}

Chang, Che-Wei ^{[1
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, Dept Elect & Comp Engn, Taipei 106, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2018年 / 65卷 / 08期

关键词：

Analog-to-digital converter (ADC); digital-to-analog converter (DAC); domino; ping-pong; successive-approximation register (SAR); 40-NM CMOS; SINGLE-CHANNEL;

D O I：

10.1109/TCSII.2018.2801295

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a 6-bit domino successive approximation register (SAR) analog-to-digital converter (ADC). The proposed domino-SAR ADC architecture provides high-speed domino operation and the offset immunity of SAR ADCs. The ping-pong operation enacts a master clock sampling scheme to achieve a sampling rate of 13 GHz. A prototype ADC chip was fabricated using a 55-nm CMOS technology. The chip consumes a total power of 3.5 mW from a 1.2-V power supply. The measured peak SNDR and SFDR are 33 and 48 dB, respectively. The peak effective number of bits is 5.2 bits, equivalent to the figure of merit of 73 fJ/conversion step.

引用

页码：999 / 1003

页数：5

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