Steamroller Module and Adaptive Clocking System in 28 nm CMOS

被引：27

作者：

Wilcox, Kathryn ^{[1
]}

Cole, Robert ^{[1
]}

Fair, Harry R., III ^{[1
]}

Gillespie, Kevin ^{[1
]}

Grenat, Aaron ^{[2
]}

Henrion, Carson ^{[3
]}

Jotwani, Ravi ^{[2
]}

Kosonocky, Stephen ^{[3
]}

Munger, Benjamin ^{[1
]}

Naffziger, Samuel ^{[3
]}

Orefice, Robert S. ^{[1
]}

Pant, Sanjay ^{[4
]}

Priore, Donald A. ^{[1
]}

Rachala, Ravinder ^{[2
]}

White, Jonathan ^{[1
]}

机构：

[1] Adv Micro Devices Inc, Boxboro, MA 01719 USA

[2] Adv Micro Devices Inc, Austin, TX 78735 USA

[3] Adv Micro Devices Inc, Ft Collins, CO 80528 USA

[4] AMD, Low Power Adv Dev Grp, Ft Collins, CO USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 01期

关键词：

28 nm CMOS; flip-flops; high-frequency CMOS design; microprocessors; power efficiency;

D O I：

10.1109/JSSC.2014.2357428

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work describes the physical design implementation of the AMD "Steamroller" module and adaptive clocking system that are both integral pieces of the AMD Kaveri APU SoC which was implemented using a 28 nm high-K metal gate Bulk CMOS process. The Steamroller module occupies 29.47 mm(2) and contains 236 million transistors. Various aspects of the core design are covered including the power and timing methodologies as well as design challenges moving from 32 nm SOI to 28 nmBulk CMOS. Adaptive clocking, one of the key features used for core power efficiency, is described in detail.

引用

页码：24 / 34

页数：11

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