A NOVEL SEU, MBU AND SHE HANDLING STRATEGY FOR XILINX VIRTEX-4 FPGAS

被引：28

作者：

Iturbe, X. ^{[1
]}

Azkarate, M. ^{[1
]}

Martinez, I. ^{[1
]}

Perez, J. ^{[1
]}

Astarloa, A. ^{[2
]}

机构：

[1] IKERLAN IK4 Res Alliance, Embedded Syst on Chip Grp, JM Arizmendiarrieta 2, Arrasate Mondragon 20500, Basque Country, Spain

[2] Univ Basque Country, Appl Elect Res Team, Dept Elect & Telecommun, ES-48013 Bilbao, Spain

来源：

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS | 2009年

关键词：

RELIABILITY;

D O I：

10.1109/FPL.2009.5272410

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

This paper presents a new Single Event Upset (SEU), Multiple Bit Upset (MBU) and Single Hardware Error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional Triple Module Redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable TMR architecture, designed under both spatial and implementation diversification premises. Moreover, since the strategy works on the device's bitstream domain, the basis for Virtex-4 FPGAs bitstream definition are also shown.

引用

页码：569 / +

页数：2

共 33 条

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[10] Xilinx推出Virtex-4系列多平台FPGA
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