A 1-V 5.2-GHz CMOS synthesizer for WLAN applications

被引:32
作者
Leung, GCT [1 ]
Luong, HC [1 ]
机构
[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China
关键词
clock generation; integer-N; low power; low voltage; oscillator; phase-locked loop (PLL); receiver; synthesizer; transceiver; VCO; WLAN;
D O I
10.1109/JSSC.2004.835830
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-mum CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm(2).
引用
收藏
页码:1873 / 1882
页数:10
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