Analytic Design of on-Chip Spiral Inductor with Variable Line Width

On-chip spiral inductors with variable line width layouts are known for their high quality factor (Q-factor). In this paper, we present an analytical approach to facilitate the design of such inductors. Based on an analysis of ohmic and eddy-current losses, we first derive an analytical formula for the metal resistance calculation of a spiral inductor. By minimizing the metal resistance, a simple design equation for finding the proper line width of each coil is then presented. Several 0.18 mu m CMOS spiral inductors are investigated, via electromagnetic simulations and experimental studies, to test the proposed resistance calculation, as well as the variable line width design method. It is found that the developed resistance calculation can effectively model the metal-line resistance of a spiral inductor. Moreover, the inductor with a variable line width obtained using the proposed method can significantly improve the Q-factor with little compromise to inductance, which validates the capacity of the developed variable line width design technique. Since the proposed approach can be carried out using analytical calculations, it may be a more efficient design method than those previously reported in the literature.