共 66 条
[1]
GARNET: A Detailed On-Chip Network Model inside a Full-System Simulator
[J].
ISPASS 2009: IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE,
2009,
:33-42
[2]
Alazemi F., 2018, 2018 IEEE INT S HIGH
[3]
ANJAN KV, 1995, ACM COMP AR, P201, DOI 10.1109/ISCA.1995.524561
[4]
[Anonymous], 2017, ON CHIP NETWORKS
[5]
[Anonymous], 2002, Interconnection Networks: An Engineering Approach
[6]
Balkind J., 2016, OPENPITON OPEN SOURC
[7]
Besta M, 2018, ACM SIGPLAN NOTICES, V53, P43, DOI [10.1145/3296957.3177158, 10.1145/3173162.3177158]
[8]
The PARSEC Benchmark Suite: Characterization and Architectural Implications
[J].
PACT'08: PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES,
2008,
:72-81
[9]
Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718
[10]
Chen C.-H., 2016, THESIS MIT THESIS MIT