Low-Jitter All-Digital Phase-Locked Loop with Novel PFD and High Resolution TDC & DCO

A low-jitter and wide output frequency range ADPLL was proposed in this paper. The adopted PFD based on sense-amplifier flip-flop (SAFF) can effectively improve the jitter performance. The novel DCO with cascading structure consists of a coarse-tuning delay chain and a fine-tuning interpolator, obtaining both wide frequency tuning range and high resolution. A time-amplifier based sub-exponent TDC was also designed with a minimum resolution of 1.25ps and a total conversion range of 2.5 ns. The proposed ADPLL was designed in SMIC 0.18 mu m CMOS process. The output frequency of the ADPLL ranges from 0.64 to 1.44 GHz with a 40MHz reference frequency. When the output frequency is 1.28GHz, the peak-to-peak and rms jitters are 22.3ps and 2.1ps respectively. The maximum power consumption is 24.43mW at (1.8v, 1.44GHz). With respect to the recently proposed high-performance ADPLLs, the proposed ADPLL shows advantages in smaller area, lower jitter and wider output frequency range.