A model for timing errors in processors with parameter variation

Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for the worst case. Unfortunately, this approach has the potential to nullify much of the upcoming gains of shrinking technologies. To help understand this problem, we introduce a novel high-level and easy-to-apply model of how parameter variation affects timing errors in microprocessors. The model successfully predicts the probability of timing errors under different process and environmental conditions for both SRAM and logic units. Circuit designers can apply the model at design time to improve yield, and computer architects can use it to design processors that improve performance.