An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel

被引:7
|
作者
Yang, Jianxiao [1 ]
Geller, Benoit [1 ]
Li, Meng [2 ]
Zhang, Tong [3 ]
机构
[1] Univ Paris Saclay, Dept U2IS, ENSTA ParisTech, F-91120 Palaiseau, France
[2] IMEC, B-3001 Heverlee, Belgium
[3] Rensselaer Polytech Inst, Dept Elect Comp & Syst Engn, Troy, NY 12180 USA
关键词
Bit error rate (BER); channel ergodic capacity; channel model; channel outage capacity; channel outage probability; error correction code (ECC); nonvolatile memory (NVM); operation failure rate; read operation; spin-torque transfer magnetic random access memory (STT-MRAM); write operation; RANDOM-ACCESS MEMORY; STATISTICAL DESIGN; FAILURE; CIRCUIT;
D O I
10.1109/TVLSI.2015.2436370
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Spin-torque transfer magnetic random access memory (STT-MRAM) has emerged as a promising nonvolatile memory technology, with advantages, such as scalability, speed, endurance, and power consumption. This paper presents an STT-MRAM cell operation channel model with write and read operations for information theorists and error correction code designers. This model considers the effects of process variations and thermal fluctuations and considers all principle flaws during the fabrication and operation processes. With this model, evaluations are not only made for the write channel, the read channel, but also the write and read channel with metrics, such as operation failure rate, bit error rate, channel ergodic capacity, and channel outage probability at certain outage capacity. Moreover, it is proved that the distributions of written-in bit states are not uniformly distributed and are proportional to their respective write success probabilities. Finally, simulation results show that practical code rates and code block lengths can guarantee reliable performances only if the operation success rate difference between state 1 and state 0 is small enough.
引用
收藏
页码:979 / 991
页数:13
相关论文
共 50 条
  • [1] Basic principles of STT-MRAM cell operation in memory arrays
    Khvalkovskiy, A. V.
    Apalkov, D.
    Watts, S.
    Chepulskii, R.
    Beach, R. S.
    Ong, A.
    Tang, X.
    Driskill-Smith, A.
    Butler, W. H.
    Visscher, P. B.
    Lottis, D.
    Chen, E.
    Nikitin, V.
    Krounbi, M.
    JOURNAL OF PHYSICS D-APPLIED PHYSICS, 2013, 46 (07)
  • [2] A Novel STT-MRAM Cell With Disturbance-Free Read Operation
    Huda, Safeen
    Sheikholeslami, Ali
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2013, 60 (06) : 1534 - 1547
  • [3] Simulation study on the information storage mechanism of STT-MRAM
    Hu Zuoqi
    Liang Wen
    Xu Jian
    Yu Fafa
    Cao Hua
    Lu Jingjing
    Li Xixi
    Miao Xiangshui
    2013 13TH NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), 2013,
  • [4] Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM
    Zhang, Liuyang
    Kang, Wang
    Zhang, Youguang
    Cheng, Yuanqing
    Zeng, Lang
    Klein, Jacques-Olivier
    Zhao, Weisheng
    2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2015, : 461 - 466
  • [5] Novel dual power hybrid write operation structure for STT-MRAM
    Jia, Xiangjian
    Cheng, Guanxi
    Zhang, Guangjun
    Jiang, Yanfeng
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2025, 112 (04) : 617 - 631
  • [6] Basic principles of STT-MRAM cell operation in memory arrays (vol 46, 074001, 2013)
    Khvalkovskiy, A. V.
    Apalkov, D.
    Watts, S.
    Chepulskii, R.
    Beach, R. S.
    Ong, A.
    Tang, X.
    Driskill-Smith, A.
    Butler, W. H.
    Visscher, P. B.
    Lottis, D.
    Chen, E.
    Nikitin, V.
    Krounbi, M.
    JOURNAL OF PHYSICS D-APPLIED PHYSICS, 2013, 46 (13)
  • [7] A Multilevel Cell for STT-MRAM Realized by Capping Layer Adjustment
    Wang, Mengxing
    Peng, Shouzhong
    Zhang, Yue
    Zhang, Yu
    Zhang, Youguang
    Zhang, Qianfan
    Ravelosona, Dafine
    Zhao, Weisheng
    IEEE TRANSACTIONS ON MAGNETICS, 2015, 51 (11)
  • [8] Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell
    Prajapati, Sanjay
    Verma, Shivam
    Kukarni, Anant Aravind
    Kaushik, Brajesh Kumar
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2019, 18 : 1005 - 1014
  • [9] STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks
    Thi-Nhan Pham
    Quang-Kien Trinh
    Chang, Ik-Joon
    Alioto, Massimo
    IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2022, 12 (02) : 569 - 579
  • [10] Switching Time and Stability Evaluation for Writing Operation of STT-MRAM Crossbar Array
    Lim, Hyein
    Lee, Seungjun
    Shin, Hyungsoon
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (10) : 3914 - 3921