A PRNG circuit on PLD with feature of low-power, high-speed, and various generation of random number sequence

被引：0

作者：

Sato, Tomoaki ^{[1
]}

Kikuchi, Kazuhira ^{[1
]}

Fukase, Masa-aki ^{[1
]}

机构：

[1] Hirosaki Univ, Bunkyo-cho 3, Hirosaki, Aomori 036-8561, Japan

来源：

TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4 | 2006年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The design of PLD (Programmable Logic Devices used for various applications needs both high-speed and low-power operation. One of the design methods suited to this requirement is wave-pipeline technique. In this paper, we describe the wave-pipelining of PLD-design. This is applied to PRNG (Pseudo-Random Number Generator) circuit that is a sequential circuit. According to the result of the gate level simulation, the waved- PRNG circuit contributes to speed-up and low-power operation. In addition, this circuit is able to easily generate various random number sequences by controlling the operation clock frequency.

引用

页码：1340 / +

页数：2

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