Wordlength optimization of a pipelined FFT processor

This paper describes the optimization of the word lengths in an 8k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. According to the specification, input and output word lengths are 12 bits but improved performance can be achieved by using a longer wordlength internally. Increased wordlength means increased size, both for memory and arithmetic operations. Since the FFT processor uses targe memories, especially in the early stages, it is especially important to keep wordlength short in the beginning of the pipeline. Finding a good trade-off between precision and size is a difficult problem and it is not reasonable to solve analytically. Simulations using a C-model are therefore used to find an acceptable solution. The simulations show that a good solution is obtained by starting with 12 bits and gradually increasing the wordlength up to 16 bits. The final result is rounded back to 12 bits. This is a good trade-off between precision and complexity.