A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

被引：3

作者：

Gonzalez-Diaz, Victor R. ^{[1
]}

Munoz-Pacheco, Jesus M. ^{[1
]}

Espinosa-Flores-Verdad, Guillermo ^{[2
]}

Sanchez-Gaspariano, Luis A. ^{[3
]}

机构：

[1] Benemerita Univ Autonoma Puebla, Fac Elect, 4 Sur 4 Col Ctr, Puebla, Mexico

[2] Inst Nacl Astrofis Opt & Electr, Luis Enrique Erro 1, Tonantzintla Puebla, Mexico

[3] Univ Politecn Puebla, Tercer Carril Ejido Serrano, San Mateo Cuanala Puebla, Mexico

来源：

RADIOENGINEERING | 2016年 / 25卷 / 01期

关键词：

Frequency synthesizers; fractional; modeling; sigma-delta; phase noise; Verilog-A; PHASE NOISE; MULTIPLIER; LOOP;

D O I：

10.13164/re.2016.0089

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthesizer simulation is compared with state of the art Verilog-A descriptions showing a reduction of nearly 20 times. In addition, experimental results of a fractional frequency synthesizer are compared to the simulation results to validate the proposed model.

引用

页码：89 / 97

页数：9

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