Hybrid Latch Flip-Flop with improved power efficiency

被引：38

作者：

Nedovic, N ^{[1
]}

Oklobdzija, VG ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, Adv Comp Syst Design Lab, Davis, CA 95616 USA

来源：

13TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/SBCCI.2000.876032

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An improved design of a Hybrid Latch Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in total Power-Delay-Product improvement of about 20%. It also exhibits better soft-clock edge properties compared To the original circuit. This is accomplished by careful design of keeper Elements and introducing the feedback path to suppress unnecessary transitions in the circuit. New design introduces insignificant area increase.

引用

页码：211 / 215

页数：5