A low-power clock frequency multiplier

A low-power output feedback controlled frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. It uses N voltage controlled delay lines (VCDL) to multiply the input clock frequency by a factor of N/2. This frequency multiplier is less susceptible to jitter-accumulation. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 27% to 36% less power than other similar circuits. In addition, the proposed circuit can be easily programmed for generating various output clock frequencies.