An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology

被引：5

作者：

Matsuno, Tetsuro ^{[1
]}

Fujimoto, Daisuke ^{[1
]}

Kosaka, Daisuke ^{[2
]}

Hamanishi, Naoyuki ^{[3
]}

Tanabe, Ken ^{[3
]}

Shiochi, Masazumi ^{[3
]}

Nagata, Makoto ^{[1
,2
]}

机构：

[1] Kobe Univ, Grad Sch Syst Informat, Kobe, Hyogo 6570013, Japan

[2] AR Tec Corp, Higashihiroshima 7390005, Japan

[3] Toshiba Co Ltd, Kawasaki, Kanagawa 2120001, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 06期

关键词：

noise emulation; substrate noise; power supply noise; signal integrity; substrate coupling; power integrity; SIMULATION;

D O I：

10.1587/transele.E93.C.820

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm(2) in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

引用

页码：820 / 826

页数：7

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