Variable supply-voltage scheme for low-power high-speed CMOS digital design

被引：160

作者：

Kuroda, T ^{[1
]}

Suzuki, K

Mita, S

Fujita, T

Yamane, F

Sano, F

Chiba, A

Watanabe, Y

Matsuda, K

Maeda, T

Sakurai, T

Furuyama, T

机构：

[1] Toshiba Corp, Syst ULSI Engn Lab, Kawasaki, Kanagawa 210, Japan

[2] Toshiba Micro Elect Corp, Syst LSI Dev Div, Kawasaki, Kanagawa, Japan

[3] Toshiba Corp, Semicond Grp, Kawasaki, Kanagawa 210, Japan

[4] Univ Tokyo, Inst Ind Sci, Tokyo, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 03期

关键词：

Buck converter; low power CMOS circuits; low threshold voltage; low voltage;

D O I：

10.1109/4.661211

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-mu m CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

引用

页码：454 / 462

页数：9

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