DrAcc: a DRAM based Accelerator for Accurate CNN Inference

被引：95

作者：

Deng, Quan ^{[1
]}

Jiang, Lei ^{[2
]}

Zhang, Youtao ^{[3
]}

Zhang, Minxuan ^{[1
]}

Yang, Jun ^{[4
]}

机构：

[1] Natl Univ Def Technol, Coll Comp, Changsha, Hunan, Peoples R China

[2] Indiana Univ Bloomington, Sch Informat & Comp, Intelligent Syst Engn, Bloomington, IN USA

[3] Univ Pittsburgh, Comp Sci Dept, Pittsburgh, PA 15260 USA

[4] Univ Pittsburgh, Elect & Comp Engn Dept, Pittsburgh, PA 15260 USA

来源：

2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2018年

基金：

美国国家科学基金会;

关键词：

D O I：

10.1145/3195970.3196029

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Modern Convolutional Neural Networks (CNNs) are computation and memory intensive. Thus it is crucial to develop hardware accelerators to achieve high performance as well as power/energy-efficiency on resource limited embedded systems. DRAM-based CNN accelerators exhibit great potentials but face inference accuracy and area overhead challenges. In this paper, we propose DrAcc, a novel DRAM-based processing-in-memory CNN accelerator. DrAcc achieves high inference accuracy by implementing a ternary weight network using in-DRAM bit operation with simple enhancements. The data partition and mapping strategies can be flexibly configured for the best trade-off among performance, power and energy consumption, and DRAM data reuse factors. Our experimental results showthat DrAcc achieves 84.8 FPS (frame per second) at 2W and 2.9x power efficiency improvement over the process-near-memory design.

引用

页数：6